PDA Chips

PDA chips and PDA design.

Early pocket computers and PDAs were built using traditional CPU chips, with much attention to power saving design. Companies who designed the earliest ones (Psion, Hewlett Packard, Sharp) tended to use full CMOS versions of older chips, run the clocks slow, and use ASICs to cut the size and add needed functions. It was only from perhaps 1995 that chips designed specifically for PDA use really started to appear in common use.


Code named OCP, or "One Chip PDA", the PR30100 is a mixed signal digital and analog chip, low cost, and in a low profile 100 pin LPQF package released in late 1995. Based on the MIPS 3000 32 bit RISC architecture, it runs at 3.3 volts, with a total power consumption around 150 mW. It has five power modes, going down to a "coma" mode that uses less than 30uA. It needs external memory, clock crystal, I/O buffers, loudspeaker, keyboard and IrDA components. All on board clocks are derived from a standard 32,768 kHz clock crystal, which provides an 18.432 MHz internal clock.

The compromises include no multiply accumulate, and only 1 kbyte instruction and data caches. The CPU core is fully static, to enable it to be disabled for various sleep modes. Indeed the CPU is normally stopped, and is active only to process interrupts. The bus interface unit allows 8, 16 and 32 bit data, with programmable wait states and page mode access. It supports two 16 bit PCMCIA I/O cards as well as memory. Theoretical address space is 4 Gbytes. The chip includes a DMA arbiter, timer module, infrared module, UART, I/O module, and touch screen module.

It uses relatively expensive static memory chips externally, rather than DRAM. There are independent DMA channels for video, sound, and UART. Power sequences include "dead" (does a reset on start), "coma" (no functions, 30 uA drain), "sleep" (software wakeup), "doze" (full Vcc power applied, CPU and clock are powered down, but the PLL is running to avoid wakeup delays), "full" (everything runs, but modules can be powered down under software control).

The I/O module can handle up to 10 bidirectional I/O pins and 16 multifunctional I/O pins, programmable as input or output ports. Any port can be powered down independent of the rest. The IR module has logic to interface to external LED and phototransistor ciruits for remote control or as IrDA data ports. The consumer side remote control includes Philips RC5 and RC6 protocols. Loudspeaker module includes drivers for a 32 ohm speaker, output of 2 V p-p adjustable in 32 steps from 0 to -45 dB. It includes an 8 bit DAC runing up to 15 kHz. Video supports several varieties of LCD, 4 bit split, 4 bit non split, and 8 bit non split, and colour displays, however there are only 4 bits for video output, so an external 4 bit register is required for multiplexing to 8 bit data. 4 or 16 gray scales are supported, and 8 bit per pixel colour mode (3 bits or red, 3 or green, 2 of blue). Gray scale is done by varying the duty cycle, so a monochrome display can be used to give the appearance of gray. The touch screen module has a connection for a 4 wire resistive touch screen, and includes a 10 bit ADC. It includes a power save mode so that it is only active when the pressure sensor is active. An analog multiplexor lets the 10 bit ADC monitor other system voltages such as from batteries, thermistors and so on.

Philips also have a $8 chip, the UCB1100H, which includes most of the analog modules of the PR30100, for designers perhaps using a different CPU. It includes a 12 bit audio codec, 14 bit telecom codec, four channel ADC, and touchscreen support.

The Philips PR31100 is more advanced than the PR30100, with a 40 MHz MIPS core and 4 kbyte instruction cache. Data cache is still 1 kbyte, as on the 30100. this core includes the MAC unit for DSP tasks. The 208 pin LQFP chip includes LCD control, UART, IrDA, CHI, SPI, digital I/O and SIB bus. Its memory controller handles SRAM, ROM, DRAM, EDO DRAM, SDRAM and flash memory. Power consumption is 165 mW in sleep mode (RTC and interrupt logic active), 40mW in doze mode, and 363mW in full operation. Philips also license their V.32bis softmodem for this chipset. The LCD support extends to 1024 by 1024 pixels. The system includes seven bidirectional I/O lines, and 32 bidirectional multifunction lines.

The RISC core has a five stage execution pipeline, and two cycle load and branch instructions, with most other instructions one cycle. The compilers will usually find an instructtion to execute while the CPU does a load or branch, but if not, a hardware interlock stalls the pipeline, rather than bloat the code with no-ops.


With the Series 5, Psion started using an Advanced Risc Machines (ARM) 710 processor, the http://www.cirrus.com/products/overviews/ps7110.html from Cirrus Logic. This 208 pin VQFP operates at 18.432 MHz at 3 volts, roughly equivalent to a 33 MHz Intel 486. however it is an ultra low power consumption device, designed to operate from AA or AAA batteries. Average power consumption is 20 mA, idle is 5 mA, 3 mA in standby. It has an 8 kbyte four way set associative cache, DRAM controller for four banks of 32 bit by 256 Mbyte DRAM, ROM/SRAM and flash memory control, synchronous serial interface for SPI or Microwire, 36 bits of general purpose I/O, a 16C550 style UART, SIR 9600-115.2 kbps infrared encoder, DC-DC converter interface with two 96 kHz outputs, an LCD controller.


Advanced Risc Machines design cores, which are then built by its licencees including SAtmel, Cirrus Logic, Fujitsu, IBM, Mitel, LG Semicon, LSI, Lucent, Nat Semi, NEC, OKI, Samsung, Sharp, TI, Toshiba and VLSI.

The range includes ARM7, ARM9, ARM10 and StrongARM. They all have 31 general purpose registers, with 16 visible. A four processor cycle fast interrupt uses seven private registers for state saving. User and supervisor mode. The Thumb extensions for all models uses a 16 bit instruction subset that are transparently expanded within the pipeline, reducing code overhead.

The ARM7TDMI core have a three stage pipeline, and a simplified MMU. The ARM9 have a five stage pipeline, and a Harvard bus. Intel own the StrongARM architecture, which has about four times the performance of the ARM7 architecture.

There is an ARM7TDMI core with provision for decoding a 48kHz MP3 stream if you have a 29 MHz clock and one cycle memory. I get the impression this was with hand assembler work rather than a DSP.

ARM 9E core incorporates direct Java bytecode execution and single instruction multiple data instructions (SIMD), for multimedia and signal processing. The ARM JVM is invoked with a new BXJ instruction, which enables a front end processor that converts Java byte codes to ARM instructions. The first four registers are used as a Java expression stack cache.

Check various White Papers at www.arm.com, also www.jeditech.com and www.picoturbo.com

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ericlindsay.com -> palmtop -> pdachips

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